Portfolio
I am drawn to all things Computer and Software Engineering, especially embedded systems, algorithm design, high-performance computing, and artificial intelligence.
My experience spans closed-loop embedded control systems, hardware-in-the-loop development, HPC development, RISC-V/MIPS processor design, and reinforcement learning.
🎓 B.S. Computer Engineering and Computer Science, Northeastern University 2026
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Led a 6-person team, designing the full power and control stack: 3-phase full-wave rectifier, MPPT load control, and a closed-loop PID pitch control system driven by tachometer feedback. Regulated rotor speed across 5–15 mph wind. Placed 4th of 32 teams at the DOE Collegiate Wind Turbine Competition 2026.
PEAK Award-funded independent research on a backscatter system that modulates ambient Wi-Fi signals for passive data transmission. Designed RF filtration, a custom encoding/decoding protocol, and a custom antenna. Mentored by Dr. Stefano Basagni and featured in the NU COE Spotlight.
Three-layer computer vision pipeline combining GroundingDINO bounding boxes, segmentation masks, and CoTracker3 point tracking to keep focus on an onboard photodiode target. Drives a closed-loop PID turret actuation system that aligns laser placement with live tracking coordinates.
NURobotics project building a delta 3D printer from scratch. Designed and software-tested a CadLab PCB that interfaces an STM32 with stepper motor drivers, and wrote C++ firmware that synchronizes three steppers to execute parallel kinematic motion.
Designed and trained two RL agents (tabular Q-Learning and Double DQN) to act as market makers in a custom trading environment. Engineered a reward function balancing profit against inventory risk over a 25-action bid/ask offset space. DQN delivered ~4× higher profit (680.71 vs 169.77) at ~20× the compute cost, quantifying the tabular-vs-deep-RL tradeoff.
Surveyed and synthesized 12 research papers spanning 2005–2025 to trace how Fast Fourier Transform implementations have evolved alongside HPC hardware.
Two systems-level projects: a Unix-style FUSE file system in C++ with block-storage architecture, nested directories, bitmap resource tracking, and file I/O syscall handling; and a full CPU datapath implemented in SystemVerilog/Verilog using both RISC-V and MIPS instruction sets.
★★★
Jan 2025 - Jun 2025
Jan 2024 - Jun 2024
Apr 2023 – Dec 2023
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