Project
Literature Review: Progression of the Use of High-Performance Computing for Fast Fourier Transforms from 2005-2025
- HPC
- FFT
- Literature Review
- Research
This paper covers two decades of FFT optimization across HPC hardware, including CPU cache autotuning, GPU shared-memory optimization, distributed multi-node scaling, Tensor Core reformulations, and mixed-precision communication compression. Key findings include that GPU acceleration shifts the FFT bottleneck from an arithmetic/computational issue to interconnect latency being dominant cost (97% of runtime on Summit). Additionally, slab decomposition was revived as the correct choice for dense GPU systems after a decade of pencil-decomposition dominance, and that numerical precision has evolved from a single compile-time setting to independently tunable parameters at the compute, communication, and accumulation layers.
Overview
Surveyed and synthesized 12 research papers spanning 2005–2025 to trace how Fast Fourier Transform implementations have evolved alongside HPC hardware.
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